The PDP-15 was DEC's last 18-bit computer system and the only one implemented with integrated circuits. This new machine was faster and less expensive than its predecessors and had the added sophistication of a separate I/O processor to the CPU. Over 400 of these machines were ordered in the first eight months of production.
More PDP-15's were built and sold than any of the 18-bit machines DEC, several incarnations including some which used a PDP-11 as a front end. Apparently the cancellation of the PDP-15 came as a great surprise to the "Tiger Team" who worked on it, although considering its general poor benefit compared to comparable performance PDP-11's it wasn't surprising.
PDP, standing for "Programmable Data Processor", was one of the major family of computers produced by Digital Equipment Corporation (DEC).
In 1957, Ken Olson and Harlan Anderson founded Digital Equipment Corporation (DEC). DEC's initial capital was at $100,000, and 70% of the company was owned by American Research and Development Corporation.
With
facilities in an old woolen mill in Maynard Massachusetts, DEC's first product
was a line of transistorized digital "systems modules" based on the modules
used in building TX-2 at Lincoln Labs, which were plug-in circuit boards with
a few logic gates per board. Starting in 1960, with
PDP-1, DEC finally began to sell computers. Soon after this, there were enough
users that DECUS, the Digital Equipment Computer User's Society was founded.
After PDP-1, DEC built a number of different computers under the PDP label, with a huge range of price and performance. The largest of these are fully worthy of large computer centers with big support staffs. Some early DEC computers were not really built by DEC. With the PDP-3 and LINC, for example, customers built the machines using DEC parts and facilities. Here is the list of PDP family of computers:
Model | Date | Price (US$) | Bus Width (bit) | Number Produces | Comments |
---|---|---|---|---|---|
PDP-1 | 1960 | 120,000 | 18 | 50 | DEC's first computer |
PDP-2 | N.A. | 24 | - | Never built, prototype only maybe | |
PDP-3 | N.A. | 36 | One built by a customer*, not by DEC | ||
PDP-4 | 1962 | 60,000 | 18 | 45 | Predecessor of PDP-7 |
PDP-5 | 1963 | 27,000 | 12 | 1,000 | The ancestor of PDP-8 |
PDP-6 | 1964 | 300,000 | 36 | 23 | A big computer, most built for MIT |
PDP-7 | 1965 | 72,000 | 18 | 120 | Widely used for real-time control |
PDP-8 | 1965 | 18,500 | 12 | ~ 50,000 | The smallest and least expensive PDP |
PDP-9 | 1966 | 35,000 | 18 | 445 | An upgrade of the PDP-7 |
PDP-10 | 1967 | 110,000 | 36 | * ~ 700 | A PDP-6 follow-up, great for timesharing |
PDP-11 | 1970 | 10,800 | 16 | > 600,000 | DEC's first and only 16-bit computer |
PDP-12 | 1969 | 27,900 | 12 | 725 | A PDP-8 relative |
PDP-13 | N.A. | - | Bad luck? There was no such machine :^p | ||
PDP-14 | A ROM-based programmable controller | ||||
PDP-15 | 1970 | 16,500 | 18 | 790 | A TTL upgrade of PDP-9 |
PDP-16 | 1972 | N.A. | 8/16 | ? | A register-transfer module system |
Model | Hardware | Software |
---|---|---|
PDP-15/10 (basic paper tape system) | Central processor; 4-Kword memory; Teleprinter | Assembler; Editor; Debugger; Utilities |
PDP-15/20 (keyboard monitor using DECtape file system) | Central processor; 8-Kword memory; Extended arithmetic; Paper tape; DECtape; Teleprinter | Keyboard monitor; FORTRAN IV; FOCAL; PIP*; Utilities |
PDP-15/30 (background/foreground) | Central processor; 16- Kword memory; Extended arithmetic; Automatic Priority Interrupt; Memory protection; Clock; Paper tape; DECtape; 2 teleprinters | B/F monitor; FORTRAN IV ; FOCAL ; PIP*; Utilities |
PDP-15/35 | (PDP-15/30 with disks) | |
PDP-15/40 (Disk based background/ foreground) | Central processor ;24- Kword memory ;Extended arithmetic; Automatic Priority Interrupt; Memory protection; Clock; Paper tape; DECtape; 524- Kword fixed head disk; 2 teleprinters | Disk B/F monitor ; FORTRAN IV ; FOCAL PIP* ; Utilities |
PDP-15/50 | 16-Kword memory | |
PDP-15/76 | 15/40 plus PDP-11 | 11-based file and I/O device management |
PDP, standing for "Programmable Data Processor", was one of the major family of computers produced by Digital Equipment Corporation (DEC).
MTBF: | 5400 hours |
Memory cycle time: | 5 us |
Memory accesses/second: | 1.25 million |
Multiply/divide time: | 4.5/4.5 us |
Memory size: | 4, ..., 131 Kwords |
Product life: | 7 years |
Power: | 2875 W |
Weight: | 750 lb = 340.2 kg |
Size: | 69x21x28 inch = 175x53x71 cm |
Volume | 23.5 ft3 = 0.66 m3 |
Logic technology: | 7400, 74H00 series integrated circuits |
Logic speed: | 10, 20 MHz |
Module Size: | 2.25, 5, 10 (X 3.875) (Same as PDP-9) |
Transistors, diodes, ICs: | 350, 200, 3.4 K |
Unlike its predecessors, the PDP-15 was designed to provide a range of systems with both hardware and software. While early 18-bit machines had evolved to include several configurations, the notion of a planned range for PDP-15 systems was explicit from the start. As it turned out, the PDP-15 evolved too, and over a considerably larger range than was anticipated. The "PDP-15 Family" table above shows the range of systems that eventually developed; of these, only the models up through 15/40 were in the original plan.
As
the industry always seek new machines with better performance/cost than the
predecessor, the new semiconductor technology, transistor-transistor logic
(TTL) gave PDP-9 a great boost in terms of packing density. Thus, PDP-15 was
packaged with the 7400 and 74H00 series of TTL integrated circuits (IC) that
permitted clock speeds of 10 to 20 MHz, and was produced at lower costs than
discrete circuits used in PDP-9. The higher packing density of the TTL IC
technology also gave PDP-15/10 the smallest size (see the figure on the right)
among the 18-bit series machines while providing a number of options and additional
features including and additional instruction set with an index and limit
register for multiprogramming.
However, the new TTL technology had one major drawback - the old discrete transistor technology had used -3 volt and ground signals, while the new TTL technology used +5 volt and ground. Therefore, level converters must be added on the I/O bus in the existing peripherals in order for them to work with new peripherals.
In addition to the cost improvements anticipated from the use of integrated circuits, it was also hoped that new memory systems available would offer both cost and performance improvements.
With the new memories and changes in addressing capabilities through the Index Register and relocation options, memory size could be expanded to 131 Kwords. A separate control unit, called the I/O Processor, handled the bookkeeping for the I/O channels and I/O Bus. The PDP-15 memory is contrasted with the PDP-1 memory in the table below:
PDP-1 | PDP-15 | PDP-15 (late) | |
---|---|---|---|
Year | 1960 | 1968 | 1972 |
Stack Size | 4 Kwords | 4 Kwords | 24 Kwords |
Cycle time | 5 us | 800 ns | 960 ns |
Words/cabinet | 12 Kwords | 48 Kwords | 96 Kwords |
Electronics | 1/3 cabinet | 1/12 cabinet | 1/24 cabinet |
Configuration | 3D stack | 5 planes, 4 bits/plane Planar stack |
20 bits/plane Planar stack |
Core size | 30 mil | 18 mil | 18 mil |
Wires/core | 4 | 3 | 3 |
The PDP-9 instruction compatibility was achieved with three minor exceptions about which no complaints were received. Compatibility for I/O devices was achieved by changing the receiver/driver modules to provide the required conversions back and forth between the older peripherals and the new PDP-15 I/O Bus.
The PDP-15 instruction set is compatible with that of PDP-9. This was achieved
by three minor exceptions about which no complaints were received. Compatibilty
for I/O devices was achieved by changing the receiver/driver modules to provide
the required conversions back and forth between the older peripherals and
the new PDP-15 I/O bus.
The PDP-15 design goal of better maintainability was partially achieved by equipping the logic with a means of monitoring 400 signal points. This feature was combined with a single step feature which permitted troubleshooting from the console without the use of an oscilloscope. As it turned out, the single step feature was used in frequently because of the training required to use it properly.
The register transfer structure of the PDP-15 processor (see the diagram on the left) was based on elements and features used in earlier designs and had a basic data path which permitted the results from any of the 11 registers to be read into the arithmetic unit and then back into the registers. In order to achieve high speed operation, a number of separate registers (such as the Step Counter, the Program Counter, and the Multiplier-Quotient registers), operated in parallel with the basic data path. In this way, significant overlap occurred, permitting the 800-nanosecond cycle time. The contrast between this design and the PDP-4 design is noteworthy. The PDP-4 had only four registers in the basic machine, but the use of integrated circuits in the PDP-15 permitted more registers to be used without so much concern for cost.
The first major extension of the PDP-15 was the addition of the Floating-Point Processor (see the figure below) to enable it to perform well in the scientific/computation marketplace using FORTRAN and other algorithmic languages. With the addition of the Floating-Point Processor, the time for a programmed floating-point operation was reduced from 100-200 microseconds to 10-15 microseconds, giving nearly a factor of 10 increase in FORTRAN performance - depending on the mix of floating-point operations.
Of the systems listed, the PDP-15/76 was one of the most interesting. A simplified block diagram of the final evolved state of the PDP-15/76 is shown in the figure on the right.
CLICK
to enlarge
The first PDP-15 was shipped in February 1970, 18 months after the project had started. A number of difficulties had been encountered, including personnel turnover, that caused a two- month slip. However, the project at first customer ship was within the budget and, by 1977, 790 machines had been shipped - more than the total of all other DEC 18-bit machines. Apparently the cancellation of the PDP-15 came as a great surprise to the "Tiger Team" who worked on it, although considering its general ungainliness compared to comparable performance PDP-11's it wasn't surprising.
Currently, under a project that aims to somehow "preserve" the computing's history, the DEC PDP family of processors are being restored and simulated. So far, there has been a couple of software for simulators of PDP series under development. For further information about this project, please refer to [3] and [9].
All the above information is obtained/excerpted from:
I'd also like to owe my appreciation to my friend, Liu Li, who helped me in the search of information with regard to PDP-15 and other PDP family members.
This page is edited by Wu Yinghui Freddie (a.k.a. Flying) for CS3220 web assignment 1, part 2 on 14 September 2000.